This application claims the priority of Japanese Patent Application No. 10-228665 filed on Jul. 29, 1998, which is incorporated herein by reference.
1. Field of the Invention
This invention relates to a silicon epitaxial wafer and a production method therefor and particularly, to high precision control of surface roughness of a silicon epitaxial layer through realization of uniform temperature distribution in a surface of a silicon wafer.
2. Description of the Prior Art
A design rule of a semiconductor device has already been reached to a subquarter micron level in a practical aspect. As an electric charge handled in a semiconductor device is decreased with progress in miniaturization, even a small number of minute defects in the vicinity of a surface of a silicon single crystal substrate have a possibility of giving a fatal influence on device characteristics larger than in the past: deterioration in performances of a bipolar circuit and a CMOS circuit has especially been problematic.
Therefore, it is expected that, hereinafter, a silicon epitaxial wafer produced by growing a silicon epitaxial layer on a silicon single crystal substrate in a vapor phase will increasingly be used instead of the silicon single crystal substrate, which is produced in a process in which a silicon single crystal ingot pulled from a melt is sliced and a slice is mirror-polished. In the following description, a silicon single crystal substrate and a silicon epitaxial wafer are generically called as a silicon wafer.
High level uniformity of thickness distribution is required for a silicon epitaxial wafer. The thickness distribution uniformity may alternatively be expressed by a flatness of a silicon epitaxial layer which is grown on a silicon single crystal substrate since the silicon single crystal substrate is originally high in flatness. The reason why the high level flatness is required is that a wavelength of exposure light which has been used in photolithography in recent years is shorter down to the far-ultra violet region and a depth of focus has greatly been reduced, so that there arises a necessity to earn any amount of a process margin. Such a requirement for high level flatness is strengthened more and more as a diameter of a silicon wafer is increased from a current 200 mm to 300 mm or more.
A structure of a single wafer type vapor phase thin film growth apparatus 20 is shown as an example in FIG. 8. In the apparatus, a silicon wafer W is singly disposed in a process vessel 21 made of transparent quartz and vapor phase growth of a thin film is performed while the silicon wafer W is heated from above and under by radiation of infrared lamps 29a, 29b. The infrared lamps 29a are an outside group and the infrared lamps 29b are an inside group.
The interior of the process vessel 21 is partitioned into an upper space 21a and a lower space 21b by a susceptor 25 on which a silicon wafer is disposed. A raw material gas which is introduced together with H2 gas, a carrier gas, through a gas supply port 22 into the upper space 21a flows in a direction of an arrow A in the figure while forming a near laminar flow along a surface of the silicon wafer W and then discharged from an exhaust port on the other side. A purge gas which is H2 gas under higher pressure than that of the raw material gas is supplied into the lower space 21b. The reason why the purge gas is under the higher pressure is to prevent the raw material gas from flowing into the lower space 21b through a gap between the process vessel 21 and the susceptor 25.
The lower space 21b contains support means made of quartz for supporting the susceptor 25 by the rear surface and lift pins 28 for loading and unloading of a silicon wafer W on the susceptor 25.
The support means is constructed from a rotary shaft 26 and a plurality of spokes 27 which radially branch away from the rotary shaft 26. Vertical pins 27b, 27c are provided to the far end of each spoke 27 and the top end of the rotary shaft 26 and the fore ends of the vertical pins 27b, 27c are respectively engaged in recesses 25c, 25d formed in the rear surface of the susceptor 25 for supporting the susceptor 25. The rotary shaft 26 is rotatable by drive means, not shown, in a direction of an arrow C in the figure.
The head of each of the lift pins 28 is enlarged in diameter and is rested while hanging on a tapered side wall of a through-hole 25b formed in the bottom surface of a pocket 25a of the susceptor 25 for disposing a silicon wafer W therein. The shaft portion of each lift pin 28 is inserted through a through-hole 27a which is formed by boring the middle portion between both ends of a spoke 27 and each lift pin 28 is designed to be vertically hung down in a stable manner.
A silicon wafer W is loaded on and unloaded from the susceptor 25 by vertical movement of the support means. For example, when the silicon wafer W is unloaded from the susceptor 25, the support means is moved downward and the tail ends of the lift pins 28 are directly put into contact with the inner surface of the lower space 21b of the process vessel 21 as shown in FIG. 9. With such encouraged conditions, the lift pins 28 push up the rear surface of the silicon wafer W with the heads, thereby floating the silicon wafer W upward from the pocket 25a. Thereafter, a handler, not shown, is inserted in a space between the susceptor 25 and the silicon wafer W and the silicon wafer W is handed over or received and further transported.
A susceptor 25 is usually made from graphite base material coated with a thin film of SiC (silicon carbide). The reason why graphite is chosen as base material is that though it is related with the fact that heating for vapor phase thin film growth apparatuses in the early stage in development was mainly conducted by high frequency induction heating, in addition graphite has merits such as a high purity product being easy to be obtained, being easy to be machined, a thermal conductivity being excellent, being hard to be broken and the like. However, graphite is a porous material mass and therefore has problems such as there being a possibility to release occluded gas during process, the surface of a susceptor being changed into SiC through a reaction between graphite and a raw material gas in the course of vapor phase thin film growth and the like. From such reasons, it is generalized that the surface of graphite is covered by a SiC film before use. A SiC thin film is usually formed by CVD (a chemical vapor deposition method).
A material of the lift pins 28 is also graphite as base material coated with SiC as in the case of the susceptor 25.
While a requirement for a flatness of a silicon epitaxial wafer has increasingly been severer every year, there has been found that even with a single wafer vapor phase thin film growth apparatus having a structure mentioned above, whose structural materials are improved, differences in thickness between positions in the surface of an epitaxial layer are not avoided according to a specific area in the surface. Especially when a thickness of a silicon epitaxial layer exceeds about 8 xcexcm, there is a trend that differences in thickness between positions in the surface of a silicon epitaxial layer are increased to a level which is unfavorable for practical use.
A film thickness distribution of a silicon epitaxial layer observed by the inventors is shown in FIGS. 10A to 10C, wherein the silicon epitaxial layer with p type conductivity and a resistivity of 10 xcexa9xc2x7cm was grown on a p+ type silicon single crystal substrate with a diameter of 200 mm, a main surface of a (100) plane and a resistivity of 0.01 xcexa9xc2x7cm to 0.02 xcexa9xc2x7cm to a target thickness 15 xcexcm. FIG. 10A shows a measurement direction for a thickness distribution; a direction which faces to a notch N which show a crystallographic orientation is called a vertical direction and a direction which intersects perpendicularly to the vertical direction is called a lateral direction. FIG. 10B is a film thickness distribution vs. a distance in the lateral direction from the center of a silicon epitaxial wafer EW. FIG. 10C shows a film thickness distribution vs. a distance in the vertical direction from the center of a silicon epitaxial wafer EW.
As can be clear from the figures, there is a trend that thickness of a silicon epitaxial layer is decreased at the center.
Since flatness is extremely large to be about 0.3 xcexcm in SFQD (SEMI M1-96) according to the definition by SEMI (Semiconductor Equipment and Materials International) thanks to the decrease in thickness, a flatness-related failure rate sometimes exceeds 4% in production of silicon epitaxial wafers. The SFQD according to the definition by SEMI is, when the entire surface of a wafer is segmented into cells each of 20 mm square, an absolute value of the maximum difference in height between a reference plane which has been obtained by the best fit method and a peak or a valley which occurs in each cell.
It was newly found by the inventors that a similar trend was also observed in FIG. 11 showing a result of measurement with a laser scattered light detection apparatus of a surface roughness distribution in the surface of the silicon epitaxial layer.
A laser scattered light detection apparatus is an apparatus by which magnitudes of a particulate and surface roughness are detected through measurement of an intensity of scattered light which is obtained in scanning on a silicone wafer with laser light. An intensity of scattered light is expressed in a unit of ppm. For example, 0.5 ppm shows that scattered light with an intensity of 0.5 part of incident light 1,000,000 parts is measured. Since an intensity of scattered light is proportional to surface roughness, it is understood that when an intensity of scattered light is larger, convexity and concavity are relatively larger in height and depth.
A laser scattered light detection apparatus can measure on the entire main surface of a silicon wafer, but since irregular reflection from a chamfered portion at a level which cannot be neglected is concurrently measured in the peripheral area of the silicon wafer, measurement values which are obtained in the peripheral area of about several mm in width are usually excluded.
In FIG. 11, the surface of a silicon epitaxial wafer EW can be categorized into 4 regions A to D according to magnitudes of surface roughness in a broad sense. The A region occupies three arc-like parts in the peripheral portion of the wafer and the arc-like parts are almost equal in shape and area; and the B region comprises insular parts located inside disconnections of the A region as centers, wherein the regions A and B have scattered light intensities as large as 0.345 ppm to 0.365 ppm, and it is understood therefore that there occurs relatively large surface roughness in the regions. On the other hand, the C region occurs in a circular shape in the central portion of the wafer; and the D region occurs in dots in the vicinity of the disconnections of the A region, wherein the regions C and D have scattered light intensities as small as 0.330 ppm to 0.335 ppm, and it is understood that there occurs relatively small surface roughness in the regions.
Values of surface roughness in the surface of a silicon epitaxial wafer EW are understood to have a dispersion of 0.035 ppm in terms of a scattered light intensity from a difference between the maximum (0.365 ppm) and the minimum (0.330 ppm) in scattered light intensity.
As mentioned above, in FIG. 11, as well, which shows a distribution of surface roughness of a silicon epitaxial wafer EW, there is observed a trend in which surface roughness is smaller in the center of the silicon epitaxial wafer as in the case of FIGS. 10 B, C.
However, a change in film thickness cannot directly be estimated from surface roughness. The reason why is that surface roughness is mainly dependent on a temperature distribution in the surface of a silicon wafer, whereas a change in film thickness is affected by not only a temperature distribution in the surface of a silicon wafer, but a supply distribution of a raw material gas on the surface.
In any case, when application of a design rule equal to or less than 0.13 xcexcm to a semiconductor process in the future is imagined, the above mentioned thickness distribution cannot be accepted in a practical aspect.
It is accordingly an object of the invention to provide a silicon epitaxial wafer in which not only uniformity of surface roughness of its silicon epitaxial layer is improved but distributions of flatness and film thickness in its surface are also improved and a production method for the silicon epitaxial wafer.
A silicon epitaxial wafer of the invention has a silicon epitaxial layer whose surface roughness distribution in its surface, which is calculated based on all measurements of surface roughness by a laser scattered light detection method excluding measured values which are respectively included within a cumulative frequency of 0.3% in the upper and lower end sides of all the measurements, is suppressed to be equal to or less than 0.02 ppm.
Exclusion of measurements which are respectively included within a cumulative frequency of 0.3% in the upper and lower end sides is equivalent almost to exclusion of measurements which fall outside the range of xxc2x13"sgr" of all the measurements (x is the average of all the measurements and a is a standard deviation).
The inventors have obtained findings that in production of such a silicon epitaxial wafer, a better result can be realized not only by improving a shape of support means made of quartz to omit the vertical pin 27c located in the central portion but by shifting a contact position of the far end (corresponding to a vertical pin 27b which is described above) of each of support members (corresponding to the spokes 27 which are also above described) with the rear surface of a susceptor further toward the outer periphery thereof compared with conventional and the invention has been proposed based on the findings. At this point, a distance between the outer peripheral edge of the susceptor and a contact position of the far end of each support member therewith is set to a value at which a decrease in temperature of the peripheral portion of a silicon wafer from the maximum temperature in the surface of a silicon wafer is suppressed to be equal to or less than 7xc2x0 C.
The susceptor is rotated about a rotary shaft and when heating means is a plurality of infrared lamps which are arranged around a central axis, the central axis is shifted eccentric to the rotary shaft of the susceptor, thereby making it possible for radiation heat of the heating means to reach even portions, from under, which have been shielded by support means in the prior art. Therefore, a local decrease in temperature in the surface of the susceptor can be alleviated, thereby making it possible to prevent decrease in film thickness at a position corresponding to the local decrease in temperature of the silicon wafer on the susceptor.
Besides, an influence of the support members can also be alleviated by increasing a distance between the rear surface of the susceptor and the support members compared with the prior art. The distance is set to a value at which a difference in temperature between the maximum and minimum in the surface of the silicon wafer can be suppressed to be equal to or less than 7xc2x0 C.
As can be clear from the above description, since, in a vapor phase thin film growth apparatus of the invention, improvement on a shape and size of support means is made and a change in relative position of the susceptor to the heating means according to a necessity is effected, a temperature distribution of a susceptor heated by radiation from heating means is optimized, so that not only is uniformity of surface roughness of a silicon epitaxial layer on a silicon wafer disposed on the susceptor improved, but flatness and film thickness distributions in the surface are also improved.
The invention relates to a technique to better a practical performance of a single wafer type vapor phase thin film growth apparatus which is expected to be main stream of its kind in company with a change toward a silicon wafer with a larger diameter and especially, the technique is effective for production of a high quality silicon epitaxial wafer and an industrial value thereof is extremely highly recognized in the semiconductor production field.